Digital (RTL) Design

Our company can offer digital RTL design and HDL verification services for both ASIC and FPGA including RTL migration from / to ASIC and FPGA.
We can deliver efficient synthesizable, DFT friendly RTL as well as verification and validation, behavioural coverage-driven HDL test beds in System Verilog (preferred), Verilog or VHDL.

We can also handle top level integration of RTL blocks, third party IP, clock controllers, memories, with special focus on ARM Processor and AMBA AHB Integration expertise (ARM9x6, Cortex M0/M3), high speed SERDES interfaces, Ethernet MAC, PCI 33 and 66, I2C, LIN, UART, SPI, DMA controllers, SRAM, SDRAM and DDRx controllers, as well as front-to-back activities like synthesis, static timing analysis, gate level simulation, scan insertion, JTAG boundary scan and memory BIST using the most popular EDA tools (Synopsys, Cadence, Mentor …)